1. Field of the Invention
The invention relates to semiconductor memory cells and, more specifically, to memory cells for use in a memory such as a dynamic random access memory (DRAM).
2. Description of the Related Art
FIG. 1 illustrates a DRAM memory cell presently available. This memory cell is constructed from a single MOS (insulated gate) transistor Q, serving as a transfer gate, which is connected to a word line WL and a bit line BL, and a data storage capacitor C connected at its end to the transistor. The other end of the capacitor C is connected to a capacitor plate potential VPL.
For the purpose of increasing the packing density of DRAM cells and lowering cost per bit, one of the inventors of the present invention has proposed a semiconductor memory cell that has such a cascade gate type of structure as shown in FIG. 2 or FIG. 3 (U.S. application Ser. No. 687,687).
The DRAM cell shown in FIG. 2 has cascade-connected MOS transistors Q1 to Q4 and data storage capacitors C1 to C4 having their respective ends connected to ends of the transistors Q1 to Q4. By turning on/off the transistors Q1 to Q4 in a predetermined sequence, stored data on the capacitors C1 to C4 can be read out onto a read/write node N1 in a sequence beginning with the capacitor C1 nearest to the end of the cascade connection, i.e., the node N1, or data at the node N1 can be written onto the capacitors C1 to C4 in a sequence beginning with the capacitor C4 farthest from the node N1.
In the DRAM cell shown in FIG. 3, a MOS transistor Q5 is further connected between one end of the transistor Q4 in the DRAM cell of FIG. 2 and a second node N2. With this type of DRAM cell, by turning on/off the transistors Q1 to Q5 in a predetermined sequence, stored data on the capacitors C1 to C4 can be read out onto the node N1 in a sequence beginning with the capacitor C1 nearest to the node N1, or data at the node N2 can be written onto the capacitors C1 to C4 in a sequence beginning with the capacitor C1 nearest to the node N1.
Such a cascade gate type of memory cell as shown in FIG. 2 or FIG. 3 is capable of storing data bit by bit. In an array of the memory cells, only one cell-to-bit-line contact is needed for every plural bits. The array can therefore realize much higher packing density than a DRAM using an array of conventional single-transistor single-capacitor memory cells and reduce cost per bit drastically.
FIGS. 4 and 5 are a plan view and a sectional view of the cascade gate cell of FIG. 2 which are disclosed in the U.S. application described previously. In these figures there is illustrated a case where the cascade gate cell is implemented as a stacked capacitor cell structure and used in an open bit line type of DRAM cell array in which capacitors are disposed in the neighborhood of intersections of word lines and a bit line.
In FIGS. 4 and 5, 50 denotes a semiconductor substrate, 52 denotes a cell active region in which the active regions (each consisting of a source, a drain and a channel region) of four transistors Q1 to Q4 are disposed linearly in the major surface of the semiconductor substrate, WL1 to WL4 denote gates (word lines) of the four transistors Q1 to Q4, 531 to 534 designate storage nodes of four data storage capacitors C1 to C4, 541 to 544 denote contacts between the storage nodes of the capacitors C1 to C4 and the sources of the transistors Q1 to Q4, 55 denotes a contact (bit line contact) between a bit line BL and an end of the cell active region (the drain region of the transistor Q1), 56 denotes a gate insulating layer, 57 denotes an interlayer insulating layer, 58 denotes an insulating layer of each of the capacitors C1 to C4, 59 denotes a plate electrode of the capacitors C1 to C4, 60 designates an interlayer insulating layer, and 51 designates a field isolation region for providing electrical isolation between memory cells which are arranged side by side in the direction in which the cascade-connected transistors are arranged.
With the cascade gate type of cell described above, when stored data on the capacitors C1 to C4 are read out onto the node N1 in sequence, a capacitor (for example, C1) which has been read from remains electrically coupled to the node N1. Thus, data read out of another capacitor (for example, C2) would also be distributed to the capacitor C1. If, in this case, the capacitors C1 to C4 are equal to one another in capacitance, a variation in voltage at the node N1 when the capacitor C1 is read from is the greatest, and the voltage variations when the capacitors C2, C3 and C4 are read in sequence decrease gradually. In an extreme case, since readout charges from the capacitor C4 are distributed to the capacitors C1 to C3, a voltage variation at the node N1 may become so small as to develop data readout errors.
In view of this point, the inventors of this application have proposed a semiconductor memory cell which permits voltage variations at the node when stored data on capacitors are read in sequence to be made substantially equal to one another (U.S. application Ser. No. 833,045).
This memory cell is characterized in that a plurality of data storage capacitors in a cascade gate type of cell are given a certain rule for their capacitance values. For example, the capacitance values of the capacitors C1 to C4 may be given a rule relating to the order of data readout, i.e., the order in which the capacitors are read from. If the capacitors are set to have capacitance values according to the order of data readout so that the capacitor that is read first has a minimum value, gradual decrease in voltage variations at the node when the capacitors are read from in sequence can be moderated or avoided. Thus, the voltage variations can be made substantially equal to one another, permitting data readout errors to be avoided.
If, however, the field oxide film 51 is used to provide isolation between memory cells as shown in FIG. 5 when an array of cascade gate cells is created, such field oxide films will be scattered in the area in which gate lines (word lines WL1 to WL4) of the memory cell MOS transistors Q1 to Q4 are arranged regularly, spoiling the pattern regularity on the substrate. If there were discontinuous points in a pattern, difficulties would arise in the IC manufacturing process, adversely affecting the pattern density.
In addition, at the top of the oxide film 51 the pattern flatness is lost, adversely affecting polysilicon lines and aluminum lines formed over the oxide layer.
An example of a conventional DRAM cell which uses an interelement isolation technique differing from field oxide films is disclosed in an article entitled "A 1-Mbit CMOS Dynamic RAM with Design-For Test Function" by Hugh Mcadams et al., IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, OCT. 1986, Page 640. In this example, electrical isolation between a DRAM cell capacitor and a bit line is provided by a polysilicon line set at ground potential.
Moreover, as shown in FIGS. 4 and 5, the bit line contact 55 will also spoil the pattern regularity on the substrate. That is, charge storage conductors 531 to 534 of the capacitors C1 to C4, which are made of, for example, polysilicon, are provided on the source regions of the transistors Q1 to Q4, but there is no charge storage polysilicon on the drain region of the transistor Q1.
Furthermore, the bit line BL is brought in direct contact with the drain region of the transistor Q1. Thus, a contact hole for the direct contact must be formed deep in the interlayer insulating layer 57. This makes the manufacturing process difficult and has an adverse influence on the increasing of the pattern density.
As described above, the presently proposed cascade gate type memory cells have room for improvements in isolation between memory cells or contact at an end of a memory cell.